The present invention relates to an improved structure of a lateral channel type junction type FET (JFET) or a static induction transistor (SIT).
Silicon carbide (SiC), which has a dielectric breakdown field about 10 times as large as that of silicon (Si), is a material that reduces the loss because it can reduce the thickness, and increase the density, of the drift layer that withstands the voltage. Power semiconductor devices using SiC include a junction type FET (JFET) and a static induction transistor (SIT). An example of an SIT that utilizes the characteristics of SiC is the structure described in “Back-gate 4H-SiC JFET fabricated on n-type substrate” in Extended Abstracts for the 61st Autumn Meeting, 2000, The Japan Society of Applied Physics (September, 2000, Hokkaido Institute of Technology).
The structure described in that publication is that the p+ layer, which is the gate region, is formed on the n-type substrate, the n− drift layer is formed above that layer and, across the channel, the n+ drain region and the n+ source region are formed. The gate electrode is formed on the major surface of the n-type substrate, the drain electrode in the drain region, and the source electrode in the source region. An SIT is a transistor that turns on or off the current by the depletion layer extending from the gate to the channel. This transistor produces a normally off state by reducing the thickness of the n− layer even when the gate voltage is 0V.